Practical Ethernet System Implementation with FPGA – Gigabit Communication Design Based on TEMAC IP
This course introduces how to design a Gigabit Ethernet communication system using AMD FPGAs and TEMAC IP. In Vivado, we will generate and configure the TEMAC IP, connect it to the Top module, and design a hardware system capable of transmitting and receiving Ethernet frames at 1Gbps speed. We will also learn the basic concepts of the Ethernet protocol, frame structure, and debugging methods (ILA, Wireshark, etc.). We will design the ARP response and UDP transmission RTL and measure performance on a PC.
(2.7) 3 reviews
29 learners
Level Basic
Course period 12 months
실습 중심
실습 중심
이더넷
이더넷
FPGA
FPGA
verilog-hdl
verilog-hdl
Verilog HDL
Verilog HDL
ethernet
ethernet
xilinx
xilinx
vivado
vivado
실습 중심
실습 중심
이더넷
이더넷
FPGA
FPGA
verilog-hdl
verilog-hdl
Verilog HDL
Verilog HDL
ethernet
ethernet
xilinx
xilinx
vivado
vivado
