AMBA AXI4 Bus Design and FPGA Implementation — From RTL to System Integration
Learn step by step, from the fundamental principles of the AMBA AXI4 protocol to Verilog RTL design, Vivado simulation verification, and FPGA implementation. Complete a 2-Master × 2-Slave interconnect through single read/write transactions, burst transfers, multi-master arbitration, and address decoding. Furthermore, develop the foundational hardware skills needed to design SoCs that connect RISC-V CPUs with memory, DMA, and peripherals, as well as to port FreeRTOS.
1 learners are taking this course
Level Intermediate
Course period Unlimited
FPGA
FPGA
verilog
verilog
soc
soc
amba
amba
rtl
rtl
FPGA
FPGA
verilog
verilog
soc
soc
amba
amba
rtl
rtl
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