AI NPU Core Computational Unit Implemented in Verilog | 3×3 Systolic Array Hands-On Practice
This is a free hands-on course where you implement a Systolic Array—the core parallel computing architecture of AI semiconductors—directly in Verilog and verify it through Vivado simulation. Using a 3×3 Output-Stationary structure as an example, you will learn step by step, from Processing Element design to input skewing, wavefront analysis, and testbench verification, enabling you to fully understand the fundamental computational principles of AI NPUs without an FPGA board.
1 learners are taking this course
Level Basic
Course period Unlimited
FPGA
FPGA
verilog
verilog
cpu-architecture
cpu-architecture
system-verilog
system-verilog
hardware
hardware
FPGA
FPGA
verilog
verilog
cpu-architecture
cpu-architecture
system-verilog
system-verilog
hardware
hardware
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