Practical AI-Based Analog/Digital Circuit Design Automation - Industry-Level LDO/AXI-Lite IP Design and Verification

Hello. This is Coach Sam.

This time, I have significantly added practical projects to both the analog circuit design and digital circuit design courses.

This update is not just a simple addition of a few practice files. It is structured so that you don't just stop at the circuit design and simulation stages, but also experience the entire workflow—from automating repetitive tasks to verifying results and organizing them into final deliverables.

Recently, there has been an increasing trend of asking semiconductor engineers how they have actually utilized AI in their work. In the latest SK hynix recruitment application, a separate section for "Describing AI Utilization Experience" was also included.

The AI experience mentioned here does not simply refer to the experience of searching for information or writing sentences using ChatGPT.

To write persuasively, you must have experience in defining problems that occur on the job, applying AI or automation tools, and then having the engineer directly verify and improve the generated results.

The two projects added this time were designed to allow you to build these experiences firsthand.

A TSMC 0.18μm CMOS LDO design project has been added to the analog lecture.

By integrating LTspice with Python, transistor sizes and compensation circuit values are automatically adjusted, while DC Gain, UGF, and Phase Margin are repeatedly measured. The process also includes automated sizing using Optuna TPE and NSGA-II, multi-objective optimization across performance, power, and area, and verification through PVT Corners and Monte Carlo simulations.

It also includes the process of structuring circuit specifications written in natural language, analyzing results by process conditions, and connecting everything to datasheet RAG and KLayout Python automation.

Upon completing this project, you will be able to describe your experience not just as "I used AI," but through the following flow:

“I defined the problem of manual, repetitive LDO circuit sizing and simulation data organization, and automated the design exploration using Python and optimization algorithms. The results structured or explained by AI were then re-verified through LTspice PVT and Monte Carlo simulations.”

A SystemVerilog-based AXI4-Lite Slave IP design and verification project has been added to the digital lecture.

You will directly implement the AXI4-Lite Read/Write Channel FSM and 16 Memory-Mapped Registers, and verify the RTL using Verible Lint, SystemVerilog Assertion, Cocotb BFM, Scoreboard, Random Test, and Functional Coverage.

Afterwards, it connects to Quartus FPGA synthesis, Setup·Hold Timing analysis, VCD-based power estimation, GitHub Actions CI, and QoR tracking for each Git commit.

In digital projects, it is important to learn how to verify RTL and test scenarios—whether written or suggested by AI—using Lint, Assertion, Simulation, Scoreboard, and Coverage, rather than simply using them as-is.

For example, you can expand your own AI utilization experience by using AI to create drafts of AXI exception conditions or test scenarios, and then implementing them with Cocotb and SVA to analyze actual failure cases.

When preparing the SK hynix AI utilization experience section, do not simply list the names of the AI tools you used.

It is recommended to organize the content so that the following details are clearly revealed.

You should explain what repetitive tasks or technical problems you identified, at which stage you applied AI and automation, what criteria and logic you designed yourself, what simulations and metrics you used to verify the AI-generated results, and how the workflow or outcomes changed before and after the application.

Especially in circuit design roles, it is more important to demonstrate that you possess the major-specific knowledge and criteria to verify AI-generated results, rather than simply stating that you "asked AI to create the circuit."

When working on this project, don't just save the final result screen; try to record the following materials as well.

• Initially defined problem and target specifications

• Directly modified RTL or circuit parameters

• AI/automation tools used and the scope of application

• Analysis of failed results and causes

• Simulation and Verification Metrics

• Final results and comparison before and after improvement

• The rationale for modifying the AI results instead of using them as-is

Having this record will allow you to explain your role in detail not only in your self-introduction and experience description but also during interviews.

I have also reinforced the installation paths and configuration guides so that the exercises can be reproduced on other PCs.

For the analog project, I have organized the LTspice execution path, Python virtual environment, model and symbol file management, and methods for running PVT and Monte Carlo simulations.

For the digital project, I have provided detailed instructions on how to install and configure environment variables for Quartus, ModelSim, Verible, OSS CAD Suite, Icarus Verilog, Cocotb, and GNU Make.

If you are preparing for a semiconductor circuit design role, I encourage you not to stop at simply following this project, but to create your own results by directly modifying the specifications and test conditions.

What is more important than the experience of using AI is the experience of using AI to solve job-related problems and verifying those results based on engineering standards.

Please check the project files and detailed lesson notes in the lecture.

Thank you.

Best regards, Coach Sam