RISC-V CPU Design for FPGA Implementation ① Learning the RV32I Instruction Structure and Execution Principles with Python
EdgeChipLab
When you decide to build a CPU, you usually start by looking for a circuit diagram. But the moment you unfold the schematic, questions arise that you cannot answer. Why does this block need to be here? Why are there two ports for reading registers? The answer lies entirely in the instructions. Once you know what the instructions require, the circuits you need are determined. It does not work the other way around. There are already many RISC-V courses. But most of them display values on slides, say "This is how it works," and move on. Students have no way to verify whether those values are correct. This course comes with a Python instruction-execution simulator. Type run ADD, and the machine code is assembled on the spot, the 32 bits are broken down by field, and how the registers change appears on the screen. Every number in the textbook is the result of running this tool, and it can be reproduced identically on your screen. Commercial debuggers require licenses, and simulators are difficult to install. This tool only requires Python. No board, license, or installation is needed. You will execute all 40 RV32I instructions yourself without leaving out a single one, discovering along the way what the circuit needs to do.
초급
riscv, cpu-architecture, instruction-set-architecture










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