Learning RISC-V Architecture Through Debugging - Part 1

Announcement 🎯

To celebrate the launch of the first RISC-V course in Korea, we are issuing a 30% discount coupon (first 100 people).

Coupon Link: https://inf.run/cbK8L

In the latest system software industry,
the emerging RISC-V architecture

Recently, the RISC-V architecture, an open-source-based CPU architecture, has been emerging. If you look at IT-related media articles or news, you can immediately find content like the following:

• Big tech companies such as nVidia, Intel, and Qualcomm are developing RISC-V-based products (chipsets).

• The number of startups in Korea designing various chips using RISC-V is increasing, and the proportion of developing products based on RISC-V devices is rising.

• RISC-V-based CPU architectures are widely utilized when designing AI semiconductors.

• It is predicted that 15 billion RISC-V-based devices will be released by 2026.

• Graduate schools (processor design) are conducting various research projects using toolkits capable of designing RISC-V CPUs.

Embedded and system software companies are increasingly utilizing the RISC-V CPU architecture to develop products. As a result, job seekers now need to prepare for RISC-V even during technical interviews.

Background of creating this course

From a beginner's perspective, the RISC-V architecture is difficult to learn. The reasons are as follows:

• I don't know what is important among the vast amount of content that makes up RISC-V.

• I don't know which features among the contents of RISC-V are actually utilized in real-world projects.

• No matter how hard you read the RISC-V specification documents, they are difficult to understand immediately.

  
  

• It is difficult to understand what the terms used to explain RISC-V actually mean.

  
  

Compared to the Arm architecture, there is a lack of materials related to the RISC-V architecture, and the reality is that there is a shortage of resources that explain RISC-V in a specific and easy-to-understand manner. I created this lecture to resolve the difficulties that system software developers, including entry-level developers, face while learning RISC-V.

A lecture by a RISC-V expert proven through global practical experience

1. Linux Plumbers Conference Presentation: Debugging RISC-V Kernel Crashes (December 2025)

(Source: https://www.youtube.com/watch?v=LNih2OdEcYo&t=1s)

2. Book: Practical Debugging for Embedded RISC‑V (Global Packt Publishing - Scheduled for publication in November 2026)

(Source: https://www.amazon.com/Practical-Debugging-Embedded-RISC%E2%80%91V-RISCV-Based/dp/1806699354/)

Course Structure and Roadmap for Part 2 and Part 3

This lecture covers the content of Part 1, which focuses on the core features of RISC-V, out of the entire RISC-V lecture series.

• Part 1: Introduction to RISC-V, Registers, Assembly Instructions, Privilege Mode

• Part 2: Exception (Memory Abort Exception), Interrupt, PLIC (Platform-level Interrupt Controller), Calling convention (RISC-V Architecture Learned Through Debugging Part 2)

• Part 3: Virtual Memory System, Cache, Fence/Barrier, Hypervisor extension (RISC-V Architecture Learned Through Debugging Part 3)

  
  

The full RISC-V architecture course can be found in the roadmap - 'RISC-V Architecture for System Software Developers' course.

Key differentiating points of the lecture

What you will learn 📕

It explains each stage of system semiconductor development and introduces the development ecosystem related to the RISC-V architecture.

Explains in detail why you need to know the RISC-V architecture well from a practical project perspective.

It explains the registers, which are the core of the RISC-V architecture, in detail. It also explains how the registers are utilized.

We introduce the types of registers that are central to the RISC-V architecture and provide a detailed explanation of general-purpose registers.

Explains the basic functions and types of CSR (Control and Status) registers.

Explains in detail how to read and write CSR registers

We will explain the configuration and operation of registers through hands-on practice by running the TRACE32 educational program (simulator).

Explains the basic operation of assembly instructions and covers various assembly instructions. (Example: Analysis of the JAL instruction)

We explain conditional branch instructions such as BEQ and cover in detail how they are utilized in real-world projects.

We will conduct a hands-on practice session debugging assembly instructions using the TRACE32 simulator (educational version). (Educators can also follow along with the practice themselves.)

We explain the concepts of Privilege Mode and the related Privilege Level in detail.

Analyze the specifications related to Privilege Mode and explain which software runs in each Privilege Mode.

Based on my experience in book writing and lecturing,
deeper and more detailed than anyone else!

In the domestic system software field, I am an unprecedented author who has written books on 'Arm Architecture (Armv8-A, Armv7-A)' and 'Linux Kernel' (both books were selected as Excellent Academic Books by the National Academy of Sciences of the Republic of Korea), and a global author who is the first in Korea to write the book "Reverse Engineering Armv8-A Systems" (in English) through an international publisher (Packt). Above all, I am an active developer who is most well-versed in the latest system software trends (electric vehicles, system semiconductors - system software). I am also an educator who is most actively engaged in spreading knowledge in the field of system software.

• Reverse Engineering Armv8-A Systems: A practical guide to Kernel, Firmware, and TrustZone analysis (Packt Publishing: English) - Published in 2025

• Author of 'Structure and Principles of Arm Architecture for System Software Development' (2024, National Academy of Sciences Excellent Scholarly Book Award)

• 'Structure and Principles of the Linux Kernel Learned Through Debugging' (2021, National Academy of Sciences Excellent Scholarly Book Award) Author

• 'Programmers Dev Course: Linux System and Kernel Expert' Main Instructor

• June 2022, Korea Computer Congress (KCC2022) - Tutorial Presentation [Conquering the Linux Kernel Using ftrace]

• LG Electronics 'Linux Kernel' and 'Armv8 Architecture' In-house Instructor (including domestic and overseas developers) - (2020~2024)