It helped me understand how to use PL logic. I hope that you will open a lecture on how to use Zynq smoothly at the beginner and intermediate level with HLS in the future.

hotak3210195

Let's gain basic knowledge and experience in non-memory semiconductor design using Verilog HDL with industry professionals.

semisgdh

인프런 10주년! 사랑주간 전체 할인

Design Self-Study Tastebi's Practical Verilog HDL Season 1 (From Clock to Internal Memory)

Thank you so much for the course review!
I think the lecture you mentioned will be helpful if I make it.
I will use it as a reference when making future lectures.
Enjoy :)

입문

초급

중급이상

베릴로그 HDL

Verilog HDL

필드 프로그래머블 게이트 어레이

FPGA

Embedded

Before starting Seolgye Dokhakmatbi's Verilog HDL


Free Environment Setup for Practice


Design Practice with Verilog HDL (Basics)


Intermediate Design Practice using Verilog HDL


Advanced Design Practice Using Verilog HDL


In conclusion


(Appendix) Taking a Break


Project: Matbi Watch
