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[2-Week Synthesis Practice Challenge Season 2] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

Recruitment Period: 2026-01-06(Tue) ~ 2026-01-19(Mon) First-come, first-served, limited to 5 people Lecture Period: 2026-01-20(Tue) ~ 2026-02-02(Mon) Content: Hands-on practice of converting RTL-level digital circuit design code written in HDL to logic gates

MetaEncore

Verilog HDL

synthesis

digital-logic

17개 수업 학습

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Market demand for application-specific integrated circuits (ASICs) such as AI (Artificial Intelligence) and IoT (Internet of Things) is increasing, and many chips are actually being designed, but it is rare for them to lead to substantial changes in our lives.

This is because many ASIC designs are either functionally flawed or fail to meet the planned performance requirements. To enrich our lives by creating high-quality semiconductors, services that provide advanced functional and performance verification capable of handling increasingly large and complex designs are essential. MetaEncore is a company that aims to increase the number of semiconductors that benefit humanity by providing such services.

[2-Week Synthesis Practice Challenge Season 2]

Recruitment Period: 2026-01-06 9:00 AM ~ 2026-01-19 5:00 PM

Lecture Schedule: 2026-01-20 9:00 AM ~ 2026-02-02 5:00 PM

*The lecture schedule and Design Compiler Tool license period are the same.

Synthesis

What is Synthesis?

Converting Register Transfer Level designs written in HDL such as Verilog to Gate Level
Optimize the design according to constraints called Synopsys Design Constraints during the conversion process
Finally mapping to standard cells provided by the Foundry

The Importance of Synthesis Experience

Creating a Compelling Personal Statement

The industry prefers new employees with synthesis and timing verification experience.
However, gaining synthesis experience requires significant cost and time.
While the industry demands experience, offline training courses also have high competition rates.
This course provides a training environment that replicates the actual working environment used in practice.
It uses Synopsys Design Compiler, the most widely used tool in the industry.
Through this course, you will be able to create a competitive resume for offline training course selection and the job market.

Korea's First Online Lecture on Synthesis Practice

What is covered in the synthesis practice lecture

Section 1. Setting Up the Practice Environment
- You can set up the practice environment in less than 5 minutes.
Section 2. Preparing the Practice Design
- Hands-on practice on how to read RTL Design described in the provided HDL code into the Tool
- Practice the process of checking the loaded RTL Design
- Hands-on practice on methods to access each Object
Section 3. Describing Synopsys Design Constraints
- Practice declaring Clock, the core of digital circuits
- Modeling the External Environment of the Chip Practice
- Basic timing verification modifications and exceptions practice
Section 4.
- Hands-on preparation for Gate Level Compile
- Compile execution practice and comparison
- Hands-on practice with Reports that need to be checked after Compile

What You'll Gain from the Synthesis Practice Lecture

You will experience Design Compiler, which is most commonly used in practical work environments.
You can differentiate your personal statement while building competitiveness.

Prerequisites

Since the process maps circuits designed in language to Gates with 'physical substance', the following prerequisite knowledge is required
- Digital logic circuits
- CMOS Operating Principles
- Basic knowledge of the Verilog language
- [Inflearn Lecture] It is recommended to take Basic Design Synthesis Training first.
  https://inf.run/xc2V3
Linux environment
- In practice, Linux environments are used.
- Unlike Windows, it primarily uses a command-line interface to communicate with the computer.
- It's helpful to know the main commands used in Linux.
TCL for communicating with EDA tools
- It is an interpreter-based language, and most EDA tools operate with a TCL interface.
- If you want to get a job in digital circuit design, it's good to study it whenever you have time.

Reference sites for study materials related to the lectures

A blog introducing the overall content of VLSI and Digital Chip Design Flow
- https://blog.vlsi.kr
TCL, the most widely used scripting language in the PI/PD field
- https://tcltk.co.kr

1월

20일

챌린지 시작일

2026년 1월 20일 오전 12:00

챌린지 종료일

2026년 2월 2일 오전 08:00

챌린지 커리큘럼

All

17 lectures ∙ (3hr 7min)

Section 1. Preparing the Practice Environment

1 lectures ∙ (3min)

1. Lab Environment Setting
03:43

Section 2. Design Setup

6 lectures ∙ (1hr 17min)

2. Read Design Introduction
10:42
3. Read Design Practice
16:36
4. Check Design Introduction
07:42
5. Check Design Practice
17:57
6. get_* Command Practice
09:50
7. get_* Command Practice
14:44

Section 3. Synopsys Design Constraints

6 lectures ∙ (55min)

8. Clock Design Introduction
15:29
9. Clock Design Practice
07:56
10. Introduction to Boundary Constraints
08:54
11. Boundary Constraint Practice
07:27
12. Introduction to Timing Exceptions
05:49
13. Timing Exception Practice
09:36

Section 4. Compile & Report

4 lectures ∙ (51min)

챌린지에서 배워요

Experience real-world environments in advance, including Linux environments
Experience the most widely used Synthesis Tool in practice
You can write a differentiated and competitive personal statement with just one experience

Recommended for
these people

Who is this course right for?

Someone preparing for job hunting
Someone who wants to change their job to semiconductor design implementation

Need to know before starting?

Basic Flow of Digital Circuit Design
Verilog HDL
Logic Circuit
[Inflearn Lecture] Basic Design Synthesis Training (Digital Circuit Design Implementation)

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[2-Week Synthesis Practice Challenge Season 2] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

MetaEncore님과 함께해요!

Please check!

[2-Week Synthesis Practice Challenge Season 2]

Synthesis

What is Synthesis?

The Importance of Synthesis Experience

Creating a Compelling Personal Statement

Korea's First Online Lecture on Synthesis Practice

What is covered in the synthesis practice lecture

What You'll Gain from the Synthesis Practice Lecture

Prerequisites

Reference sites for study materials related to the lectures

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챌린지에서 배워요

Recommended for these people

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MetaEncore's other courses

Recommended for
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