Putting a neural network on an FPGA — it sounds familiar, but few people have actually done it.
If you want to get ahead in capstone projects, competitions, or graduation projects, you need to go beyond training a model: you must be able to build and prove for yourself how its computations actually run inside a chip. This course helps you bridge that gap between theory and physical hardware.
From reading the specifications to building a Python golden model, Machine Learning training, Verilog RTL design, and FPGA verification, you will complete a neural network accelerator (NPU) for recognizing MNIST digits written in real people’s handwriting from start to finish. From a Conv layer built with line buffers and parallel MACs, through ReLU, MaxPool, and Flatten, to fully connected layers and Argmax — you will integrate nine blocks into a single chip and prove for yourself that "the Python reference answer and the hardware output do not differ by even one bit (Bit-True)." The course also covers how to overcome that frustrating moment when the simulation runs perfectly, but the results are subtly different.
We will walk through practical know-how that general deep learning textbooks do not cover, one step at a time — including integer quantization, array-axis ordering conversions, and preventing accumulator overflow. Drawing on the trial and error I have experienced through extensive work with RISC-V CPU design and FPGA Bit-True verification, I have built those lessons into this course so that you do not have to repeat them. By the end of the course, you will have a complete hardware project in hand and be able to say, "I designed it myself and proved it."