Design Self-Study's Verilog Master Season 2 (The Ultimate Practical Coding Test: Job Change Free Pass Completed with High-Difficulty Problems)
If Season 1 was about checking your skills and solidifying the basics, Season 2 is intensive practical training focused solely on 'passing and career transitions.' Beyond simple syntax or gate-level design, you will directly design top-tier, high-difficulty modules (CDC, Synchronous/Asynchronous FIFO, AMBA APB, SPI, I2C, FIR filters, etc.) that frequently appear in coding tests and actual workflows at major corporations and foreign companies. Do you need solid design capabilities that won't waver even under a recruiter's relentless follow-up questions? This course contains all the practical know-how and ultimate coding test problems from ETA, who successfully moved from a regional university to a global semiconductor firm. In this final season, complete your career transition free pass.
41 learners are taking this course
Level Intermediate
Course period Unlimited
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L2_P08 SRAM 코드 리뷰 부탁드립니다.
`timescale 1ns / 1ps module sync_sram_ctrl #( parameter ADDR_WIDTH = 8, parameter DATA_WIDTH = 16 )(
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18 days ago
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L2_P4 data_average 코드 리뷰 및 waveform 질문 드립니다.
`timescale 1ns / 1ps module data_avg ( input logic clk, input logic rstn, in
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a month ago
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LV2-2 Patter Detector code review 부탁드립니다.
`timescale 1ns / 1ps module pattern_detector_no_fsm ( input logic clk, input logic rstn,
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a month ago
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환경 설정하는 guide 최신화 부탁드립니다.
안녕하세요,이번 강의 처음으로 수강하는 수강생인데 이전 버전의 환경 설정하는 영상이나 글 따라해도 계속 막힙니다.build시 자꾸 에러가 나오거
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a month ago
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