Design Self-Study Tastebi's Practical Verilog HDL Season 1 (From Clock to Internal Memory)
Let's gain basic knowledge and experience in non-memory semiconductor design using Verilog HDL with industry professionals.
1,698 learners
Level Basic
Course period Unlimited
(2021.11.13) Notice of update to Verilog HDL Season 1 installation video.
Hello! Design family, this is Matbi :)
Okay? As you know, I'm sure you all know that the installation videos are the hardest.
I am truly sorry to those of you who have overcome this process and are studying, and I would like to express my sincere gratitude.
In order to install smoothly using the Big Data accumulated through your blood, sweat, and tears, I found out that the following parts need to be modified.
1. Instead of GUI installation, you need to do Command Line installation.
2. When modifying the install_config.txt file, you need to turn off not only the installation path, but also the option at the very bottom. (This is the 99% chance, it takes too long ㅠ.ㅠ)
EnableDiskUsageOptimization=1 (default: on)
This
EnableDiskUsageOptimization=0 (change to off)
We will continue to evolve into a taste that continues to evolve.
Take care of your health and have fun :)
