Design Self-Study Tastebi's Practical FPGA-Based HW Accelerator Design (From LED Control to Fully Connected Layer Accelerator Design)
With the help of the design self-study taste-maker! Let's gain basic knowledge of FPGA and HW accelerator design experience.

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It's time to have your design skills evaluated.
Self-Study Design Verilog Master Season1 course has been 100% completed.
Please download the practice code again. (File name: SGDH_Verilog_Master_S1_Lecture_100%.zip)
Although it's said that employment is difficult due to AI advancement, the foundation of it all is your own skills.
You just need to build knowledge and know-how that AI cannot do or is unable to do.
Let's study together with Eta's know-how, who went from a bachelor's degree graduate through government-funded training → small and medium enterprises → large corporations → foreign companies, and enjoy a wise design life together.
Thank you.
Self-taught design taste dream.

Hello. This is Masbi from Design Self-Study.
Finally, the
📘Verilog Master Season 1course that many of you have been waiting for is now open!This course is not just a simple grammar explanation,
but a practical-focused course where you can solve problems that were actually given in interviews and coding tests
to check your digital design skills yourself and even develop practical intuition.🧩This course is recommended for these people.
Circuit design coding test preparation for majors / job seekers
Graduate student who wants to learn RTL design through hands-on practice
Engineers who want to organize Verilog to a professional level
SystemVerilog beginner who wants to implement even Testbenches
🧠Course Features Summary
Contains over 40 practical Verilog design problems
Interview-based questions, practical problems applicable to real work
Problem Introduction → Solution Time → Explanation → Waveform → Schematic Review
Content directly created, reviewed, and edited by ETA and Matbi
🗂Structure Guide
Level 0: Basic concept problems including gates, Karnaugh maps, FSM, etc.
Level 1: Practical interview preparation problems including ALU, interrupts, pipelines, etc.
Problems will continue to be updated regularly in the future.
This is the time when there are the fewest issues and you can take the course at the most affordable price.
After enrollment, it will operate with unlimited access and Q&A.Now it's your turn to
directly verify and prove your Verilog skills.Verilog is not an option, but a necessity.
Build both your foundation and practical skills with Season1,
and let's grow together in the upcoming Season2(Level 2~3).I'll see you in the lecture.
Thank you.
— From ETA & Matbi- [Important Notice] Verilog HDL Season 2, the course access period has been changed to 'unlimited'! 🎉
Hello, design family!
The course period for Verilog HDL S2 has been changed from "1 year" to "unlimited" (excluding existing B2B payments due to policy).
I sincerely thank you for trusting me and taking my class.
I don't know when I'll retire... 😭😭 (I'm still young)
Until then, we will do our best to provide unlimited access to classes and Q&A.
Thank you!! Raw milk!!


