Verilog FPGA Program 3 (DDR Controller)

The lecture has been updated.

1. FPGA Utilization with Verilog (v2.1)

   1. NRZL Decoder implementation (ch11) has been added.

   2. Important information about implementing and using FIFO.

   3. I hope it will be of great help in my practice.

2. FPGA Utilization for Zynq with Verilog (v1.2)

   1. NRZL Decoder implementation (ch14) has been added.

   2. Important information about implementing and using FIFO.

   3. I hope it will be of great help in my practice.

Those who purchased the course can download it for free from the data room.
I hope this lecture will be of great help to you.

thank you