goodman03's honest review, Design Self-Study Tastebi's Practical Verilog HDL Season 1 (From Clock to Internal Memory) course
Reviews 1
Average rating 5
Before starting this, I had jumped straight into an FPGA project first, only to find myself unable to properly read the Verilog code generated by AI. I signed up for this lecture with the mindset of never letting that happen again. It was a time where I could realize that I had many misunderstandings while actually writing code for things I had been curious about—things I had either asked AI or just briefly touched upon in school. Thank you so much for creating such a great lecture..!!
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Thank you, Eunhyuk Cho, for leaving a rating and a review. I hope the content of Season 1 helped you establish the basic flow and structure of Verilog HDL. I will be rooting for you to steadily complete the remaining 40% until the very end. Happy studying!
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