Everything is great, but it feels lacking to try to do a testbench without knowing SV. I wish you would also show it with a regular testbench in Vivado..!!

akflffltls8001

Let's build AMBA AXI4 design and VIP verification experience, foundational to SoC Bus, through self-study of design with Verilog HDL!

semisgdh

Design Self-Study Flavor's Practical Verilog HDL Season 2 (Complete Mastery of AMBA AXI4)

Thank you for leaving your feedback, miro11.
This course focuses on explaining the AXI structure and actual design flow, so some parts proceed with the assumption of an SV-based testbench. This was a direction chosen based on the nature of the course, so I hope you'll keep that in mind while taking it.
If you focus on understanding the operation and structure of AXI itself, I believe the remaining content will also be helpful.
Happy learning.

반도체

verilog

fpga

amba

임베디드

입문

초급

중급이상

베릴로그 HDL

Verilog HDL

필드 프로그래머블 게이트 어레이

FPGA

Embedded

Before starting 설계독학맛비's Verilog HDL Season2

Mastering Valid/Ready Handshake Design, Fundamental to Data Transmission

Mastering Essential Buffer and FIFO Design for Smooth Data Transfer

Mastering theory and verification environment for AXI4 Interface design

Mastering AXI4-Lite Design

Mastering AXI4-Stream Design

Conquering AXI4 Design (feat. things every design engineer must know!!)

Memory copy IP. Designing DMA (Direct Memory Access).

[Project] Let's port ""Matbi Mem copy IP"" onto FPGA! (Operation and Performance Check)

Concluding