For the theoretical part, the content can be found in the AMBA spec or Xilinx Reference manual, but when it comes to actual implementation, having reference implementations to refer to and knowing whether unknown features exist (especially in protoinst or VIP utilization) makes a huge difference, and this was very practically helpful.

hjkim99

Let's build AMBA AXI4 design and VIP verification experience, foundational to SoC Bus, through self-study of design with Verilog HDL!

semisgdh

Design Self-Study Flavor's Practical Verilog HDL Season 2 (Complete Mastery of AMBA AXI4)

hjKim, thank you for leaving such a thoughtful course review.
As you mentioned, there are parts that are difficult to grasp with just the reference manual, and I'm glad that encountering the implementations through hands-on practice was helpful. I feel especially rewarded that you found even the detailed features like protoinst and VIP utilization meaningful. I encourage you to connect what you've learned to your actual projects as well!

반도체

verilog

fpga

amba

임베디드

설계독학과 함께 Verilog HDL을 이용하여 SoC Bus의 기본이 되는 AMBA AXI4 설계와 VIP 검증 경험을 쌓아봅시다!

설계독학맛비

입문

초급

중급이상

베릴로그 HDL

Verilog HDL

필드 프로그래머블 게이트 어레이

FPGA

Embedded

설계독학맛비's 실전 Verilog HDL Season 2 (AMBA AXI4 완전정복)

설계독학맛비's Verilog HDL Season2 를 시작하기 전에

Data 전송의 기본이되는 Valid / Ready Handshake 설계 정복하기

원활한 Data 전송을 위한 필수 Buffer, FIFO 설계 정복하기

AXI4 Interface 를 설계하기 위한 이론 및 검증환경 숙지하기

AXI4-Lite 설계 정복하기

AXI4-Stream 설계 정복하기

AXI4 설계 정복하기 (feat. 설계엔지니어라면 꼭 알고 있어야하는 내용들!!)

Mem copy IP. DMA (Direct Memory Access) 설계하기.

[프로젝트] "Matbi Mem copy IP" 를 FPGA 에 올려보자! (동작 및 Performance 확인)

마치며