2025/06/15/Sun 08:04
Thank you for creating good lectures. I was always curious about how a CPU works, but after listening to all four lectures you created, I learned how it operates. I also understood Verilog much better and learned about AXI4. If you upload lectures again next time, I will listen to them right away. Thank you.

aceoftop1975

Let's build AMBA AXI4 design and VIP verification experience, foundational to SoC Bus, through self-study of design with Verilog HDL!

semisgdh

인프런 10주년! 사랑주간 전체 할인

Design Self-Study Flavor's Practical Verilog HDL Season 2 (Complete Mastery of AMBA AXI4)

Wow... I am truly grateful and touched that you listened to all 4 lectures!
To those who were curious about how the CPU actually works within a system, I feel a great sense of reward knowing it was helpful and that the planning intention of this lecture was well conveyed.
Since you've understood everything up to Verilog and AXI4, you've likely developed the core skills to immediately apply them in real-world situations :)
For the next lecture as well, I will prepare with even better content and meet you again. Thank you once again!

반도체

verilog

fpga

amba

임베디드

입문

초급

중급이상

베릴로그 HDL

Verilog HDL

필드 프로그래머블 게이트 어레이

FPGA

Embedded

Before starting 설계독학맛비's Verilog HDL Season2

Mastering Valid/Ready Handshake Design, Fundamental to Data Transmission

Mastering Essential Buffer and FIFO Design for Smooth Data Transfer

Mastering theory and verification environment for AXI4 Interface design

Mastering AXI4-Lite Design

Mastering AXI4-Stream Design

Conquering AXI4 Design (feat. things every design engineer must know!!)

Memory copy IP. Designing DMA (Direct Memory Access).

[Project] Let's port ""Matbi Mem copy IP"" onto FPGA! (Operation and Performance Check)

Concluding