I'm here to greet you in celebration of the course deadline change!
You always answer questions quickly and well, and the course content is substantial!
Now I'll go finish the final part I couldn't complete due to time constraints~

shjeong6825

Let's gain experience in designing AMBA AXI4, the foundation of SoC Bus, and VIP verification using Verilog HDL with Design Self-Study!

semisgdh

Design Self-Study Matbi's Practical Verilog HDL Season 2 (Mastering AMBA AXI4)

Haha 😊😊 Thank you for the witty greeting and the warm review!
I always tried to answer questions quickly, and feeling that way makes it even more rewarding.
I hope you complete the final section feeling good. Let's run together till the end!

반도체

verilog

fpga

amba

임베디드

입문

초급

중급이상

베릴로그 HDL

Verilog HDL

필드 프로그래머블 게이트 어레이

FPGA

Embedded

Before starting Seolgye Dokhak Matbi's Verilog HDL Season 2

Mastering the Design of Valid / Ready Handshake, the Foundation of Data Transfer

Mastering FIFO Buffer Design: Essential for Seamless Data Transfer

Understand the theory and verification environment for designing an AXI4 Interface

Mastering AXI4-Lite Design

Mastering AXI4-Stream Design

Mastering AXI4 Design (feat. Essential content every design engineer must know!!)

Designing a Mem copy IP. DMA (Direct Memory Access).

[Project] Let's load the "Matbi Mem copy IP" onto an FPGA! (Checking Operation and Performance)

Conclusion