I interned in a SoC-related department during my undergraduate years, and I remember starting without knowing anything about AMBA Specs, so I put in a lot of effort and time... I wish I had taken this lecture back then, I could have learned so much more, it's a shame 😊.. It was a really great lecture! Thank you :)


whdgns35855485

Let's build AMBA AXI4 design and VIP verification experience, foundational to SoC Bus, through self-study of design with Verilog HDL!

semisgdh

인프런 10주년! 사랑주간 전체 할인

Design Self-Study Flavor's Practical Verilog HDL Season 2 (Complete Mastery of AMBA AXI4)

Thank you so much for your valuable experience and heartfelt review.
It would be rewarding if our lecture could fill the void you felt back then, even just a little 🙏
We will continue to improve in the future to provide more informative lectures that are directly applicable to practical work.
Happy studying!!


반도체

verilog

fpga

amba

임베디드

입문

초급

중급이상

베릴로그 HDL

Verilog HDL

필드 프로그래머블 게이트 어레이

FPGA

Embedded

Before starting 설계독학맛비's Verilog HDL Season2

Mastering Valid/Ready Handshake Design, Fundamental to Data Transmission

Mastering Essential Buffer and FIFO Design for Smooth Data Transfer

Mastering theory and verification environment for AXI4 Interface design

Mastering AXI4-Lite Design

Mastering AXI4-Stream Design

Conquering AXI4 Design (feat. things every design engineer must know!!)

Memory copy IP. Designing DMA (Direct Memory Access).

[Project] Let's port ""Matbi Mem copy IP"" onto FPGA! (Operation and Performance Check)

Concluding