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์ฑ„๋„ํ†ก ์•„์ด์ฝ˜

STM32 FFT ๊ตฌํ˜„

STM32์—์„œ DSP Library๋ฅผ ์‚ฌ์šฉํ•˜์—ฌ FFT๋ฅผ ๊ตฌํ˜„ํ•ฉ๋‹ˆ๋‹ค.

(5.0) ์ˆ˜๊ฐ•ํ‰ 2๊ฐœ

์ˆ˜๊ฐ•์ƒ 100๋ช…

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alex๋‹˜์˜ ํ”„๋กœํ•„ ์ด๋ฏธ์ง€

๊ฐ•์˜ ์˜คํ”ˆ ๊ธฐ๋… 50% ํ• ์ธ ์ฟ ํฐ ์ œ๊ณตํ•˜์—ฌ ๋“œ๋ฆฝ๋‹ˆ๋‹ค.

์•ˆ๋…•ํ•˜์„ธ์š”.

Verilog๋ฅผ ์ด์šฉํ•œ FPGA ํ™œ์šฉ2 - DDR Controller

๊ฐ•์˜๊ฐ€ ์˜คํ”ˆ๋˜์—ˆ์Šต๋‹ˆ๋‹ค.

DDR Memory๋Š” ์˜์ƒ์ฒ˜๋ฆฌ์—์„œ ๋งค์šฐ ์ค‘์š”ํ•˜๊ฒŒ ์‚ฌ์šฉ๋ฉ๋‹ˆ๋‹ค.

์ด๋ฒˆ ๊ฐ•์˜๋Š” DDR Memory Controller๋ฅผ ๊ตฌํ˜„ํ•˜๋Š” ๋ฐฉ๋ฒ•์„ ์•„์ฃผ ์ž์„ธํ•˜๊ฒŒ ์„ค๋ช…ํ•˜๊ณ  ์žˆ์Šต๋‹ˆ๋‹ค.

  •  Memory IP ์ƒ์„ฑ 

  • Memory IP Simulation ํ†ตํ•œ ๋™์ž‘ ์ดํ•ด

  • ๋ฒ”์šฉ์œผ๋กœ ์‚ฌ์šฉ๊ฐ€๋Šฅํ•œ User Interface Logic ์„ค๊ณ„

  • User Interface Logic์„ ์ด์šฉํ•œ Memory ์ „์˜์—ญ read/write test

  • User Interface Logic์„ ์ด์šฉํ•œ Frame Buffer ๊ตฌํ˜„

๋ณธ ๊ฐ•์˜๋ฅผ ํ†ตํ•˜์—ฌ DDR Memory Controller๋ฅผ Master ํ•  ์ˆ˜ ์žˆ๋„๋ก ๊ตฌ์„ฑํ•˜์˜€์Šต๋‹ˆ๋‹ค.

๊ฐ•์˜ ์˜คํ”ˆ ๊ธฐ๋…์œผ๋กœ 5์ผ๊ฐ„ 50% ํ• ์ธ ์ฟ ํฐ์„ ์ œ๊ณตํ•˜์—ฌ ๋“œ๋ฆฝ๋‹ˆ๋‹ค.

๋ณธ ๊ฐ•์˜๋ฅผ ํ†ตํ•˜์—ฌ ๋งŽ์€ ๋ถ„๋“ค์—๊ฒŒ ์œ ์ตํ•œ ์ž๋ฃŒ๊ฐ€ ๋  ์ˆ˜ ์žˆ๊ธธ ๊ธฐ๋Œ€ํ•ฉ๋‹ˆ๋‹ค.

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์ถ”์šด ๋‚ ์”จ์— ๊ฑด๊ฐ• ์œ ์˜ํ•˜์‹œ๊ณ 

ํ•˜์‹œ๋Š” ์ผ๋“ค ๊ฐ€์šด๋ฐ ์ข‹์€ ์ผ๋“ค์ด ๊ฐ€๋“ํ•˜๊ธธ ๊ธฐ์›ํ•ฉ๋‹ˆ๋‹ค.

๊ฐ์‚ฌํ•ฉ๋‹ˆ๋‹ค.

 

๋Œ“๊ธ€