psh2018314072

맛비님이 제공해주신 true_dpbram.v을 테스트해보고 싶어서 다음과 같은 테스트벤치를 만들어봤습니다.
`define ADDR_WIDTH 12
`define DATA_WIDTH 16
`define MEM_DEPTH 384
module tb_true_dpbram();
reg clk;
reg addr0;
reg ce0;
reg we0;
wire q0;
reg d0;
&nbsp;
true_dpbram&nbsp;
#( .DWIDTH&nbsp; &nbsp;(`DATA_WIDTH),&nbsp;
 .AWIDTH&nbsp; &nbsp;(`ADDR_WIDTH),&nbsp;
 .MEM_SIZE (`MEM_DEPTH))&nbsp;
u_TDPBRAM(
 .clk (clk),&nbsp;
&nbsp;
 .addr0 (addr0),&nbsp;
 .ce0 (ce0),&nbsp;
 .we0 (we0),&nbsp;
 .q0 (q0),&nbsp;
 .d0 (d0),&nbsp;
&nbsp;
// no use port B.
 .addr1 (0),&nbsp;
 .ce1 (0),&nbsp;
 .we1 (0),
 .q1 (),&nbsp;
 .d1 (0)
);
&nbsp;
initial clk = 0; always #5 clk = ~clk;
initial begin
#0 addr0 = 12'b0; ce0 = 0; we0 = 0; d0 = 16'b0;&nbsp;
#10 addr0 = 12'b0010_1100_1101; ce0 = 1; we0 = 1; d0 = 16'b0000_0000_0001;
#10 addr0 = 12'b0010_1100_1101; ce0 = 1; we0 = 1; d0 = 16'b0000_0000_0001;
#10 addr0 = 12'b0010_1100_1101; ce0 = 1; we0 = 0; d0 = 16'b0;
&nbsp;
end
endmodule
그런데 q0값이 계속 unknown으로 나오는데 뭐가 잘못된걸 까요?ㅠ
&nbsp;

psh2018314072

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