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Design Self-study Taste's Bible for Practical AI HW Design, Complete Conquest of CNN Operations (Accelerator Practice Using Verilog HDL + FPGA)

[AI HW Lab3] CNN Verilog HDL Practice 4 (FPGA)

ip 패키징 질문

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패키징시 이런 문제들이 뜹니다. 해결책에 대해서 여쭤보고싶습니다.

 

[IP_Flow 19-11770] Clock interface 's00_axi_aclk' has no FREQ_HZ parameter.

 

[IP_Flow 19-2187] The Product Guide file is missing.

 

[IP_Flow 19-11888] Component Definition 'xilinx.com:user:cnn_core_test_ci3_co32_v1_0:1.0 (cnn_core_test_ci3_co32_v1_0_v1_0)': IP description "cnn_core_test_ci3_co32_v1_0_v1_0" is not meaningful: same as name or display name

verilog-hdlfpga임베디드cnn

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semisgdh님의 프로필 이미지
semisgdh
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안녕하세요 🙂

tool 관련해서는.. 저도 답이 없네요.

해결책 남겨주셔서 감사합니다!

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