[2-Week Synthesis Practice Challenge Round 5] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

Recruitment Schedule: ~ 2026-05-04(Mon) Closing for the first 5 applicants on a first-come, first-served basis Lecture Schedule: 2026-05-05(Tue) ~ 2026-05-18(Mon) Content: Hands-on practice of the process of converting RTL-level digital circuit design code described in HDL into logic gates