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start_gui source xsim.dir/tb_clock_generator/xsim_script.tcl # set_param project.enableReportConfiguration 0 # load_feature core # current_fileset WARNING: [Board 49-26] cannot add Board Part xilinx.com :ac701:part0:1.4 available at /home/rhxoguq00/tools/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/ac701/1.4/board.xml as part xc7a200tfbg676-2 specified in board_part file is either invalid or not available   WARNING: [Board 49-26] cannot add Board Part xilinx.com :zcu216ld:part0:2.0 available at /home/rhxoguq00/tools/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu216ld/production/2.0/board.xml as part xczu59dr-ffvf1760-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com :zcu670:part0:2.0 available at /home/rhxoguq00/tools/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670/2.0/board.xml as part xczu67dr-fsve1156-2-i specified in board_part file is either invalid or not available WARNING: [Board 49-26] cannot add Board Part xilinx.com :zcu670ld:part0:1.0 available at /home/rhxoguq00/tools/Vivado/2022.2/data/xhub/boards/XilinxBoardStore/boards/Xilinx/zcu670ld/1.0/board.xml as part xczu57dr-fsve1156-2-i specified in board_part file is either invalid or not available INFO: [IP_Flow 19-234] Refreshing IP repositories INFO: [IP_Flow 19-1704] No user IP repositories specified INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/home/rhxoguq00/tools/Vivado/2022.2/data/ip'. current_fileset: Time (s): cpu = 00:00:14 ; elapsed = 00:00:07 . Memory (MB): peak = 9273.348 ; gain = 411.062 ; free physical = 79 ; free virtual = 3465 # xsim {tb_clock_generator} -wdb {simulate_xsim_tb_clock_generator.wdb} -autoloadwcfg Time resolution is 1 ps create_wave_config run all $finish called at time : 100 ns : File "/home/rhxoguq00/Season 1/Matbi_VerilogHDL_Season1/chapter_1/tb_clock_generator.v" Line 32