인프런 커뮤니티 질문&답변
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베릴로그 송수신기
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송신기와 수신기를 만들려고 합니다.
송신기는 64비트 데이터를 관리하고 이를 한 비트씩 시리얼 방식으로 shift하여 송신합니다. 송신기의 FSM은 다음과 같은 상태를 가집니다:
IDLE: 송신 대기 상태.
LOAD: 데이터 로드 상태 (Payload 포함).
SHIFT: 데이터를 1비트씩 시리얼로 전송.
WAIT: 수신으로 전환 조건을 확인.
송수신 통합 구조
송신기에서 자동으로 숫자가 증가하면서 데이터가 생성되고, 비교 결과가 참이면 데이터를 수신기로 전달합니다. 이를 위해 tx, rx 모듈과 ID_Comparator를 사용합니다.
송신기의 조건은 자동으로 숫자가 올라가며, 숫자가 비교기랑 맞으면 자동으로 수신에 넘어가는걸 만들고 싶어요. 근데 잘 숫자가 자동으로 올라가는 부분과 숫자 저장하는 부분이 잘 되지 않습니다 ㅜㅜ
module Rx(clock, control, KEY0, KEY1, SW, HEX0, HEX1, HEX2, HEX3, HEX4, HEX5, LEDR);
// clock=P11, control=KEY1, KEY0=clr, SW[9]=En
input clock, control;
input KEY0, KEY1; // KEY0과 KEY1을 독립적으로 선언
input [9:0] SW;
output [0:6] HEX0, HEX1, HEX2, HEX3, HEX4, HEX5;
output [9:0] LEDR;
wire [15:0] preamble;
wire [11:0] SFD;
wire [1:0] DestinationID, SourceID;
wire [31:0] payload;
wire [2:0] state, next_s;
wire [63:0] Data;
wire trans, MS, count;
// halfsecond 모듈
halfsecond half_sec(clock, KEY0, SW[9], count);
// savedata 모듈
savedata s0(
.clock(clock),
.En(SW[9]), // Enable을 SW[9]로 연결
.control(control),
.SW(SW),
.preamble(preamble),
.SFD(SFD),
.DestinationID(DestinationID),
.SourceID(SourceID),
.payload(payload),
.state(state),
.next_s(next_s),
.Data(Data),
.LEDR(LEDR),
.MS(MS),
.count(count)
);
// transdata 모듈
transdata t0(
.clock(clock),
.clr(KEY0), // clr을 KEY0로 연결
.control(control),
.Data(Data),
.trans(trans),
.count(count)
);
// 7-segment 출력
num_7seg H0(Data[3:0], HEX0);
num_7seg H1(Data[7:4], HEX1);
num_7seg H2(Data[11:8], HEX2);
num_7seg H3(Data[15:12], HEX3);
num_7seg H4(Data[19:16], HEX4);
num_7seg H5(Data[23:20], HEX5);
endmodule
module savedata(clock, En, control, SW, preamble, SFD, DestinationID, SourceID, payload, state, next_s, Data, LEDR, MS, count);
input clock, En, control, count;
input [9:0] SW;
output reg [15:0] preamble;
output reg [11:0] SFD;
output reg [1:0] DestinationID, SourceID;
output reg [31:0] payload;
output reg [2:0] state, next_s;
output reg [63:0] Data;
output reg MS;
output [9:0] LEDR;
reg P;
reg [1:0] S;
wire match_preamble;
wire match_sfd;
wire [15:0] expected_preamble = 16'b1010101010101010;
wire [11:0] expected_sfd = 12'b101010110100;
Compare_Preamble_SFD c0(clock, SW[9], preamble, expected_preamble, SFD, expected_sfd, match_preamble, match_sfd);
parameter S0 = 3'b000, S1 = 3'b001, S2 = 3'b010, S3 = 3'b011, S4 = 3'b100, S5 = 3'b101, S6 = 3'b110, S7 = 3'b111;
always@(posedge clock or negedge En)
begin
if (!En)
state <= S0;
else if (count)
state <= next_s;
end
always@(posedge clock or posedge SW[9] or posedge SW[8] or negedge En)
begin
if(SW[9])
begin
Data <= 0;
preamble <= 0;
SFD <= 0;
DestinationID <= 0;
SourceID <= 0;
MS <= 0;
payload <= 0;
state <= S0;
P <= 1'b0;
S <= 2'b00;
end
else if (SW[8])
begin
SourceID <= SW[1:0];
MS <= SW[2];
end
else if (!En)
begin
if(state == S0)
begin
state <= next_s;
end
else if(state == S1 && P == 1'b0)
begin
preamble <= {preamble[7:0], SW[7:0]};
state <= next_s;
P <= 1'b1;
end
else if(state == S1 && P == 1'b1)
begin
preamble <= {preamble[7:0], SW[7:0]};
state <= next_s;
P <= 1'b0;
end
else if(state == S2 && S == 2'b00)
begin
SFD <= {SFD[7:0], SW[3:0]};
state <= next_s;
S <= 2'b01;
end
else if(state == S2 && S == 2'b01)
begin
SFD <= {SFD[7:0], SW[3:0]};
state <= next_s;
S <= 2'b10;
end
else if(state == S2 && S == 2'b10)
begin
SFD <= {SFD[7:0], SW[3:0]};
state <= next_s;
S <= 2'b00;
end
else if(state == S3)
begin
DestinationID[1:0] <= SW[1:0];
state <= next_s;
end
else if(state == S4)
begin
SourceID[1:0] <= SW[1:0];
state <= next_s;
end
else if(state == S5)
begin
payload <= payload + SW[7:0];
state <= next_s;
end
else if(state == S6)
begin
Data <= {preamble, SFD, DestinationID, SourceID, payload};
state <= next_s;
end
end
end
assign LEDR[2:0] = state;
assign LEDR[5:3] = next_s;
assign LEDR[8:6] = {P, S};
assign LEDR[9] = MS;
endmodule
module transdata(clock, clr, control, Data, trans, count);
input clock, clr, control;
input [63:0] Data;
output reg trans;
reg [63:0] shift;
reg en;
reg [5:0] bit_count;
output count;
halfsecond h0(clock, clr, control, count);
always@(posedge clock or posedge clr)
begin
if (clr)
begin
trans <= 1'b0;
shift <= 64'b0;
en <= 1'b0;
bit_count <= 6'b0;
end
else if (control == 0 || count == 1)
begin
shift <= Data;
en <= 1'b1;
bit_count <= 6'b0;
end
else if (en)
begin
trans <= shift[63];
shift <= {shift[62:0], 1'b0};
bit_count <= bit_count + 1;
if (bit_count == 6'b111111)
begin
en <= 1'b0;
end
end
end
endmodule
module Compare_Preamble_SFD (
input clk,
input clr,
input [15:0] received_preamble,
input [15:0] expected_preamble,
input [11:0] received_sfd,
input [11:0] expected_sfd,
output reg match_preamble,
output reg match_sfd
);
always @(posedge clk or posedge clr)
begin
if (clr)
begin
match_preamble <= 0;
match_sfd <= 0;
end
else
begin
match_preamble <= (received_preamble == expected_preamble);
match_sfd <= (received_sfd == expected_sfd);
end
end
endmodule
module num_7seg (S, HEX);
input [3:0] S;
output [0:6] HEX;
assign HEX[0] = (~S[3]&~S[2]&~S[1]&S[0])|(~S[3]&S[2]&~S[1]&~S[0])|(S[3]&~S[2]&S[1]&S[0])|(S[3]&S[2]&~S[1]&S[0]);
assign HEX[1] = (~S[3]&S[2]&~S[1]&S[0])|(S[2]&S[1]&~S[0])|(S[3]&S[1]&S[0])|(S[3]&S[2]&~S[0]);
assign HEX[2] = (~S[3]&~S[2]&S[1]&~S[0])|(S[3]&S[2]&~S[0])|(S[3]&S[2]&S[1]);
assign HEX[3] = (~S[3]&~S[2]&~S[1]&S[0])|(~S[3]&S[2]&~S[1]&~S[0])|(S[2]&S[1]&S[0])|(S[3]&~S[2]&S[1]&~S[0]);
assign HEX[4] = (~S[3]&S[0])|(~S[3]&S[2]&~S[1])|(~S[2]&~S[1]&S[0]);
assign HEX[5] = (~S[3]&~S[2]&S[0])|(~S[3]&~S[2]&S[1])|(~S[3]&S[1]&S[0])|(S[3]&S[2]&~S[1]&S[0]);
assign HEX[6] = (~S[3]&~S[2]&~S[1])|(~S[3]&S[2]&S[1]&S[0])|(S[3]&S[2]&~S[1]&~S[0]);
endmodule
module halfsecond(Clr, Clk, En, Q);
input Clk, Clr, En;
output reg Q;
reg [25:0] D;
always @ (posedge Clk)
begin
if (~Clr)
begin
D <= 25'b0;
Q <= 1'b0;
end
else if (En)
begin
if (D == (25'd24999999)) // 0.5초 주기
begin
D <= 25'b0;
Q <= 1'b1;
end
else
begin
D <= D + 1'b1;
Q <= 1'b0;
end
end
else
begin
D <= 26'b0;
Q <= Q;
end
end
endmodule
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