파운드리 & 팹리스 향 ASIC Implementation 직무 : From RTL to GDSII

This is a practical course on 'AI-based Circuit Design/Verification Automation' as required by professionals at Samsung Electronics and SK Hynix. Master the skills for LDO IP design and verification automation based on TSMC 180nm PDK, AI-based AXI-Lite RTL implementation, and Python/TCL/Batch script regression automation.

This course introduces how to design a Gigabit Ethernet communication system using AMD FPGAs and TEMAC IP. In Vivado, we will generate and configure the TEMAC IP, connect it to the Top module, and design a hardware system capable of transmitting and receiving Ethernet frames at 1Gbps speed. We will also learn the basic concepts of the Ethernet protocol, frame structure, and debugging methods (ILA, Wireshark, etc.). We will design the ARP response and UDP transmission RTL and measure performance on a PC.

This lecture implements a DDR Memory Arbiter.

In this lecture, we will understand the basic concepts and operating principles of FPGAs, and examine the advantages of FPGAs and their differences from ASICs. Next, we will explain the FPGA design process and detailed FPGA design areas. We will learn about the types and roles of FPGA development tools, and proceed with the installation of Vivado, an AMD FPGA development tool. Through a simple example design practical exercise, you will experience the FPGA design process.

Starting from the operating principles of RISC-V instructions, this is a hands-on CPU design course in which you directly design a 32-bit CPU with a five-stage pipeline, completing the process from Verilog RTL implementation and simulation verification to running it on a physical FPGA. Among the 40 RV32I instructions, 14 instructions essential for learning the core structure of a CPU are selected to progressively build TinyRV32I. You will directly design and verify the key structures that make up a real CPU, including the datapath, pipeline registers, ALU and control circuits, branches, hazards, stalls and flushes, and memory-mapped I/O. The Verilog RTL, testbenches, assembly programs, memory images, and FPGA constraint files used in the course are provided. Ultimately, you will run actual programs on an Arty S7-25 FPGA using the CPU you designed. This course does not end here. After completing the core CPU structure through TinyRV32I, the series continues as a step-by-step CPU design program in which you expand it into a Full RV32I CPU supporting all 40 RV32I instructions in the follow-up course.

This lecture implements a DDR Memory Arbiter.

If Season 1 was about checking your skills and solidifying the basics, Season 2 is intensive practical training focused solely on 'passing and career transitions.' Beyond simple syntax or gate-level design, you will directly design top-tier, high-difficulty modules (CDC, Synchronous/Asynchronous FIFO, AMBA APB, SPI, I2C, FIR filters, etc.) that frequently appear in coding tests and actual workflows at major corporations and foreign companies. Do you need solid design capabilities that won't waver even under a recruiter's relentless follow-up questions? This course contains all the practical know-how and ultimate coding test problems from ETA, who successfully moved from a regional university to a global semiconductor firm. In this final season, complete your career transition free pass.

When you decide to build a CPU, you usually start by looking for a circuit diagram. But the moment you unfold the schematic, questions arise that you cannot answer. Why does this block need to be here? Why are there two ports for reading registers? The answer lies entirely in the instructions. Once you know what the instructions require, the circuits you need are determined. It does not work the other way around. There are already many RISC-V courses. But most of them display values on slides, say "This is how it works," and move on. Students have no way to verify whether those values are correct. This course comes with a Python instruction-execution simulator. Type run ADD, and the machine code is assembled on the spot, the 32 bits are broken down by field, and how the registers change appears on the screen. Every number in the textbook is the result of running this tool, and it can be reproduced identically on your screen. Commercial debuggers require licenses, and simulators are difficult to install. This tool only requires Python. No board, license, or installation is needed. You will execute all 40 RV32I instructions yourself without leaving out a single one, discovering along the way what the circuit needs to do.

UART is the most basic and widely utilized serial communication method, making it a very suitable learning topic for beginners new to FPGA design. In this course, we will thoroughly understand the communication principles and frame structure of UART, and based on this, we will proceed with directly implementing transmit/receive logic through RTL (Register Transfer Level) design. By implementing UART on an FPGA, you can systematically develop your digital circuit design skills and gain experience verifying its operation at the actual hardware level through simulation and verification. Furthermore, by learning the method utilizing the MicroBlaze soft processor and Xilinx UART IP, you will gain a broad understanding of processor-based system design flow and interface configuration. This will enable you to acquire comprehensive development capabilities encompassing both logic design and processor design.