[2-Week Synthesis Practice Challenge Batch 6] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

Recruitment Schedule: 2026-05-05 ~ 2026-05-18 (Closes after the first 5 applicants) Lecture Schedule: 2026-05-19 ~ 2026-06-01 Content: Hands-on practice of the process of converting RTL-level digital circuit design code described in HDL into logic gates