[2-Week Synthesis Practice Challenge 3rd Batch] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

Recruitment Period: 2026-02-04(Wed) ~ 2026-03-09(Mon), limited to the first 5 applicants Lecture Schedule: 2026-03-10(Tue) ~ 2026-03-23(Mon) Content: Hands-on practice of the process of converting RTL-level digital circuit design code described in HDL into logic gates