[2-Week Synthesis Practice Challenge Season 2] Experience RTL Synthesis in a Professional Environment (Synopsys Design Compiler)

Recruitment Period: 2026-01-06(Tue) ~ 2026-01-19(Mon) First-come, first-served, limited to 5 people Lecture Period: 2026-01-20(Tue) ~ 2026-02-02(Mon) Content: Hands-on practice of converting RTL-level digital circuit design code written in HDL to logic gates